1. Field of the Invention
The present invention relates to a delay line for a ring oscillator circuit. The invention relates particularly but not exclusively to a predetermined-value delay line for a ring oscillator circuit suitable to be used in phase locking systems and the following description is made with reference to this field of application for convenience of illustration only.
2. State of the Art
As it is well known, oscillator circuits are usually realized by rings of delay stages, comprising in turn elementary delay cells, connected and driven by convenient multiplexers.
A possible application of these ring oscillator circuits is in phase locking systems used in low-voltage power supplies. In particular, these phase locking systems require stable oscillators which can be varied in frequency by a control signal. It is also possible to use ring oscillator circuits in FM demodulators, clock generators for microcontrollers and for serial transmissions.
FIG. 1 shows a ring oscillator circuit realized according to the prior art, globally and schematically indicated with 1. The ring oscillator circuit 1 comprises a plurality of cascade-connected delay stages 3, controlled by a plurality of multiplexers 2 and fed back in a ring 4 by means of a logic gate 5 and a feedback delay stage 6.
For convenience of illustration, FIG. 1 shows a ring oscillator circuit 1 comprising three elementary delay stages 3, indicated with 3-1, 3-2 and 3-3, connected by means of three multiplexers 2, indicated with 2-1, 2-2 and 2-3. A first delay stage 3-1 has an input terminal directly connected to the feedback delay stage 6 and an output terminal connected to a first input terminal of a first multiplexer 2-1, having a second input terminal directly connected to the feedback delay stage 6 by means of a first fast line 7-1.
The first multiplexer 2-1 has also a control terminal receiving a first bit C0 of a control word and an output terminal connected to a second delay stage 3-2. Similarly to the first delay stage 3-1, this second delay stage 3-2 has an output terminal connected to a first input terminal of a second multiplexer 2-2.
The second multiplexer 2-2 has a second input terminal connected by means of a second fast line 7-2 to the output terminal of the first multiplexer 2-1, as well as a control terminal receiving a second bit C1 of the control word and an output terminal connected to a third delay stage 3-3. This third stage 3-3 has an output terminal connected to a first input terminal of a third multiplexer 2-3, having in turn a second input terminal connected by means of a third fast line 7-3 to the output terminal of the second multiplexer 2-2, as well as a control terminal receiving a third bit C2 of the control word.
The third multiplexer 3-3 has also an output terminal connected to a first input terminal of the logic gate 5, having in turn a second input terminal receiving an external reset signal RESET and an output terminal connected to the feedback delay stage 6.
A clock signal CK is generated on the output terminal of the third multiplexer 2-3, corresponding to an output terminal OUT of the ring oscillator circuit 1.
Moreover, the delay stages 3-1, 3-2 and 3-3 comprise an increasing number of elementary delay cells 8, realized by single logic gates (NAND, NOR etc.), or in a ‘standard cell’, not being dedicated to any particular application. The delay stages 3-1, 3-2 and 3-3 and the corresponding multiplexers 2-1, 2-2, 2-3 form a plurality of delay lines of the ring oscillator circuit 1. In the example shown in FIG. 1 these stages and multiplexers are three, but it is possible to provide them in any number.
The ring oscillator circuit 1 realized according to the prior art is programmable by changing the control word C0-C2 sent to multiplexers 2. Reference is made to a digitally-controlled oscillator (DCO, or “Digital Controlled Oscillator”), which can be integrated in a completely digital technology and used in applications which cannot use analog circuits, such as completely digital phase locking rings.
The frequency of the ring oscillator circuit 1 is varied by dividing by a programmable number a starting frequency value. In this case, a very high starting frequency value must be provided to obtain a good resolution. The design and realization of a digital divider for a value N is not simple for the frequency values which would be required. It is also possible to realize the ring oscillator circuit 1 by using tristate elements. In this case it is, however, difficult to obtain high frequency values together with wide frequency variation ranges.
It should be noted that a delay stage realizes a desired programming delay Tp only when it is driven by a delay stage preceding it in the ring 4, driven in turn by a previous delay stage. In fact, only in this case, the load conditions applied at the input of the delay stages are the same. Actually, as it is immediately evident, the ring 4 comprises a first and a last stage having different load conditions from the one of a delay stage in the ring and they have thus slightly different propagation delay values.
In its more general form, the delay Tc of the chain of N stages 3 of the ring 4 is given by:Tc=Tp*N−k with Tp the ideal propagation delay of a stage; and k the deviation from this ideal propagation delay due to the first and last stage of the chain.
It is thus evident that, in reckoning the oscillation period of the ring oscillator circuit 1, this deviation k having to be multiplied by the number of delay stages. A reckoned period is thus obtained, which can even be considerably different from the theoretical one. Moreover, this deviation k is variable, depending on the number of delay stages being selected to obtain a desired value for the oscillator circuit oscillation period.
This is a considerable limitation of the ring oscillator circuit 1 realized according to the prior art, because an uncertainty of the obtained signal period is unacceptable in many applications.
The technical problem underlying the present invention is to provide a ring oscillator circuit, having such structural and functional features as to overcome the limits still affecting the circuits realized according to the prior art.